1. Field of the Invention
The present invention relates to a technique for communicating within or among one or more integrated circuits by means of a data bus.
2. Description of the Prior Art
An integrated circuit that includes both logic and memory portions frequently also includes a data bus for communication among the various portions. A data bus includes a given number of electrical conductors (e.g., 32) that define the maximum word size that can be transferred at one time. The simultaneous transfer of bits is sometimes referred to as a "parallel" transfer in the art. In typical prior art designs, all of the logic and memory portions of the circuit transferred the same number of bits; that is, they had the same word size. In some cases, a word was broken down into smaller portions for transfer; i.e., a 32 bit word was divided into two 16 bit segments for two sequential parallel transfers over the data bus.